Analysis of switched impedance source/quasi-impedance source DC-DC converters for photovoltaic system

ABSTRACT


INTRODUCTION
The increased use of renewable energy has been fueled by the global energy crisis [1]. One of the most important players in the battle against the energy crisis is solar energy. As shown in Figure 1, photovoltaic (PV) arrays are a low dc source voltage that requires a high step-up DC-DC converter to transform to a higher voltage level before connecting to a grid-connected inverter [2], [3]. However, a higher switching duty cycles is needed to achieve the high voltage gain, which decreases efficiency and causes inductor saturation. Traditional impedance source inverter (ZSI) has many flaws, including a high inrush current, discontinuous input current, and higher voltage stress on condensers [4]- [11] suggests quasi impedance source inverters to overcome limitations. The boost factor of the ZSI can be increased using a variety of methods. When diodes, inductors and capacitors are connected to the Z-source network, for example, a higher dc-link voltage is generated [12], [13]. A cascaded quasi-Z-source network [14] is used in the topology to achieve higher voltage gain.
Currently, research on the Z-source network focuses primarily on the conversion of DC-AC power, despite the fact that the Z-source network, with its unique advantages, can also be used in the conversion of DC-DC [15], [16]. Figure 2 depicts the initial impedance source DC-DC converter s with a 1/(1-2*D) boost factor (switch S duty cycle is D). Yu et al. [17] defined a hybrid three Z-topology boost converter that Unite traditional Z-source topology in a number of different ways. The boost factor, which is best suited to PV applications, can be greater than 1/(1-4D). The main disadvantage is that it necessitates a large number of passive materials, making it more expensive and larger in volume.  This work introduces a novel class of DC-DC converter designed for PV systems with low passive components. By connecting the standard output ports of the impedance source/quasi-impedance source topology with one more switch and diode as shown in Figure 1. When the switches are switched on, the output capacitor not only acts as the DC connection. However, it is bound in cascaded to the charging loops of the inductors. The proposed boost converter, Will achieve the identical voltage gain of 1/(1-4D) with fewer modules than the hybrid three Z-topology boost converters in lesser unit cost and high power density [17]. In another way, for the same boosting voltage, the latest topologies need a low duty ratio, resulting in smaller inductors and a lower risk of inductive saturation [18]. Figure 2(a) depicts the standard impedance source converter circuit, which includes the two inductors (L1 and L2) and two capacitors (C1 and C2) in an X-shape. Figure 2(b) indicates one switching cycle. The quasi-Z-source inverters (qZSIs) continuous current mode state consists of two states: shoot-through and non-shoot-through. Figure 2(c) represents changeable input current that can arise when the circuit starts to increase the current by turning a portion of the short zero states into open zero states depending on the load condition and capacitance value. duty cycle. As a result, the backend H-modulation Bridge's index can be tuned to a wider range. As indicated in Figure 3, there are several different types of functioning as: -Mode 1: during the Shoot-through situation, the output side of the impedance network, i.e. the inverter bridge terminals, is short-circuited by a combination of semiconductor switches (S21, S22, S23 and S24). The input diode D1 turns off during this time interval, and energy is transmitted from capacitors to inductors [19]- [22]. The stored energy is sent to the load in the inverter's next active switching states, and the input diode conducts. -Mode 2: the primary circuit alternates between two active and two zero states during the non-shootthrough condition. During this mode the diodes D1, D2, and D3 are reverse biased and switches S21 and S24 can be turned on at same time. The inductors L1 and L2 store energy while the capacitors C1, C2, and C3 are discharged, and the energy stored in capacitor C3 is supplied to the load.

MODELING THE PV CELL
A photovoltaic (PV) material is one that can convert photon into electrical energy. Electrons can be released from an atom by photons with short wavelengths. On a conductor, electrons can flow and form an electric current. The sun provides the energy required to break the bonds. This is a significant opportunity because the earth's surface receives 6000 times the total daily energy consumption. A PV module can be described using an equivalent circuit that includes a current source, a diode, and a resistor to represent internal resistance. When the sun's rays strike the solar cell, current is generated as: Where = short circuit current, = temperature constant, = irradiance, and = temperature in Kelvin. Current flowing through the diode ID determines the output current from the solar cell, and current flows to the internal resistance ℎ [2]. The equation then becomes: In (3), must be used to compute current flows in a diode.
From Figure 4, PV module output current and voltage relationship is given by (4).
From (4), the I-V characteristic curve can be obtained which gives operation of the solar panel. At fixed temperature and irradiance, the meeting of the I-V characteristic curve and the load characteristics is the solar panel's operational point. The operative position of the panel goes from zero resistance to infinite resistance, resulting in the appearance of open circuit voltage ( ) [23]- [30].
The multiplication of highest value of the voltage and current gives maximum power. As shown in Figure 5, when the panel voltage reaches voltage at maximum power ( ), a PV module operates at its maximum power. By modifying the load, the maximum power can be obtained, which will cause the current flowing in the circuit is limited and in addition to the panel voltage.

WORKING PRINCIPLE AND CIRCUIT TOPOLOGIES OF THE PROPOSED CONVERTERS
The following simulation is mainly focused on first network i.e., switched-ZSC, since the circuit configurations of the proposed three circuits are identical. The following other two SQZSCs can also be analyzed with similar technique. The critical current mode (CRM) is a subset of either the continuous conduction mode (CCM) or the discontinuous conduction mode (DCM). Two cases (Cases 1 and 2) may appear in CCM under differing combinations of inductance, duty cycle, and load resistance, but only in case 3 may appear in Discontinuous Conduction Mode. Throughout a loop, each and every circuit has different state [20], [21]. All of the circuit states are found in the two modes which are depicted in Figures 6(a)-(e) (see Appendix). In Figure 6(a) the reference directions for each variable are shown i) Case 1 -State1 → State2, ii) Case 2 -State1 → State2 → State3, and iii) Case 3 -State1 → State2 → State 3. In this state, the voltages across the three capacitors can be calculated using KVL. State1 → State2 → State3 → State4. For the sake of simplicity, assuming: i) all ideal power components; ii) L1=L2 and C1=C2 are ignored; and iii) L1=L2 and C1=C2. Figure 6(b) represents the current loop corresponding to state1, which indicates current through L1&C1 are equal. Figure 6(c) indicates path of the currents for State2. Figure 6(d) indicates the currents path in state3, further Figure 6(e) represents path of currents corresponding to State4.

IMPEDANCE NETWORK MATHEMATICAL ANALYSIS
Let us assuming that the capacitors (C1&C2) and inductors (L1&L2) have identical values. the input voltage is Vd; the output voltage Vi; series arm inductors L1 and L2; parallel arm capacitors C1 and C2. An impedance source inverter equivalent circuit model is derived from Figure 7 in (5) Where = 0 + 1 and the dc source voltage is . The average voltage of the inductors should be zero in steady state after one switching cycle (T).
Similarly, the Avg DC voltage across the inverter bridge can be determined using (8). The maximum dc-link voltage of the inverter bridge is, Boost factor is B, Output peak phase voltage of the inverter is, Here modulation index is M and source voltage = * * 0 /2 Before selecting an acceptable buck-Boost factor, the V0 can be stepped down and up (BB) . = * (range from 0 to 1) The capacitor voltage is Figure 7. Impedance source inverter equivalent circuit

EFFECT OF THE PARASITIC PARAMETERS OF THE EFFICIENCY 5.1. Power switching loss
Conduction loss and switching loss are two types of losses in power switches. The conducting loss can be measured using Figure 7.
The power switch loss can be determined by linearizing the voltages and currents of the communicate switches [20], [21] as change their states, The input power can be calculated using (11) as where the switching frequency is f s and t off and t on are the switch turn-off and turn-on delays.

Diode power loss
Reverse recovery loss and conduction loss are the two forms of diode power losses. Conduction loss is denoted by Diodes reverse recovery loss is given by, Where D1, D2 and D3 diodes and QRR1, QRR2 and QRR3 reverse recovery charge of diodes respectively.

Inductor loss
An ideal inductor has zero power loss because it has no resistance and just inductance, = 0, and no power is dissipated within the coil. A device that stores energy as an electromagnetic field and measures in henrys is known as an inductor (H), Conduction losses will occur in a practical inductor with internal resistance. So, the conduction loss can be measured, decides the key power loss. = 2 2 (20)

Capacitor loss
The capacitors total power losses are calculated as, Then, the derived total conduction losses are The input power calculated as, Following that, the proposed SZSC efficiency can be determined by using

CONTRASTS WITH PREVIOUS Z-SOURCE TOPOLOGIES
Furthermore, as shown in Table 1, the proposed topology output is differentiated to that of the converters in [17], [22]- [30]. The capacity to boost is a critical metric for assessing the efficiency of a dc-dc converter. When the voltage gain G is greater than 5, with the same duty ratio the proposed work produces a higher boost factor than the other converters. Although the boost factor is the same as in [17], which is a complicated hybrid three cascade Z-network boost converter. To put it another way, the proposed topology dramatically decreases the no. of passive elements needed to achieve the identical boosting capability. There are two advantages, the first one to decrease the probability of inductive saturation, and the second one to increase the modulation index (MI). As a consequence, when using the two-stage dc-ac conversion, a wider range can be reserved for the MI of the posterior H-bridge. Component numbers are also compared in Table 1 between topologies and the proposed one. The posterior H-bridge is replaced with a diode, output capacitor and switch in each structure to convert it to a dc-dc converter. In comparison to proposed hybrid three-Z-network boost converter, The new one has the identical 1/(1-4D) voltage gain but uses 2 fewer inductors, 4 fewer capacitors, and 1 fewer diode and adding another switch feature increases power density while lowering cost.
When the voltage gain G>5, as illustrated in Figure 8, the suggested topology produces a greater boost factor than other converters at the same duty ratio, while the boost factor is the same as in [18], which is a complex hybrid 3-Z-network boost converter. The matlab-simulink detailed specifications are given in Table 2.   No. of parallel strings of an array 2 4 No. of series connected module for string 4 5 O.C voltage (Voc) 68V 6 S.C current (Isc) 7.5A 7 Switching Frequency(fsw) 25KHZ 8 Inductors (L1=L2) 320µH 9 Capacitors (C1=C2) 340µF 10 Load resistor 100Ω 11 Output power (Pout) 440.7w

SIMULATION RESULTS
For 100V dc/ac conversion, a 215 V dc voltage output is used, and voltage input is set by connecting four PV panels in series sequence. The simulation parameters are as follows, based on the previous analyses; i) Vi is 68 volts; ii) fs is 25 kHz; and the service period is 0.2; iii) the evaluate output power is 185 was expected; iv) L1=L2=320µH, with a parasitic resistance of 28-mΩ; v) C1=C2=C3=330µF, with a 10-mΩ equivalent sequence resistance; vi) Switches S1 and S2 have an on-state resistance of 14.5mΩ; vii) The diodes D1, D2, and D3 have a forward voltage drop of 1V. Figure 9 show input inductor currents, for one, are simulated waveforms in switched ZSC/switched QZSCs as well as voltage across capacitors 215[V/div] (Vc2=Vc4=215V). Figure 10 shows the proposed converter with PV-array is operated at its MPPT under radiation level of 1000 W/m 2 , the voltage at PV-array is 68.4V with respect to time in seconds, Current at PV-array is 7A with respect to time in seconds and the power at PV-array is 478.8W (Ppv=Vpv *Ipv) with respect to time. The load draws 440.7W of power with respect to time in seconds, as shown in Figure 11.

CONCLUSION
It is suggested that a series of switched impedance source/switched quasi-ZSCs with modified topology be developed for Photovoltaic systems. By putting an extra switch and diode to ordinary ZS/qZS DC-DC converter s, the increased boost factor up to 1/(1-4D). To achieve higher voltage gain while avoiding the instability induced by inductor saturation, a short duty cycle is used. The boost ratio of the proposed converters is the same as the hybrid three Z-network boost converters. That were recently proposed, but with fewer passive components, allowing for higher power density and lower unit costs. The operating principles of these devices are detailed in this paper, as are the parameters of current and voltage, as well as conversion efficiency of the parasitic parameters the effects. Eventually, results of the simulation provided to support the properties and theoretical analysis previously mentioned.