Minimizing the switching losses in the SiC MOSFET by using buried oxide

Abstract

For optimizing the efficiency of the power switching devices, it is important to reduce the switching power losses. One method to minimize the switching power losses is to reduce the gate drain charge (QGD). In this paper, a 1.2 kV SiC MOSFET device with a buried oxide has been proposed to minimize QGD. The proposed design has been conducted by using the TCAD simulation program. The on-resistance (Ron,sp), QGD have been measured and analyzed based on the width and thickness of the buried oxide layer and compared with the measurement of traditional SiC MOSFET. The obtained results indicate that the QGD of 1.2 kV SiC MOSFET with buried oxide with WBO of 0.25 μm and TBO of 0.3 μm was reduced to about 31.3% which mean a minimize of power losses. The comparison results indicate that the proposed device with a buried oxide layer can be effectively used as an optimum solution for minimizing the power switching losses.